----------------------------------------------------------------------
-- FIR Filter implemented as a systolic array
-- James Carroll
-- BYU ECEn 620, Fall 2008
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
	use ieee.numeric_std.all;
	
entity FIRFilter is
	generic(
		word_size:integer:=32
	);
	port(
			-- Inputs
			clk : in std_logic;
	        a_0, a_1, a_2, a_3 : in signed(word_size-1 downto 0);
	       	x_in : in signed(word_size-1 downto 0);
			-- Outputs
            y_out : out signed(word_size-1 downto 0)
	);
end entity;

architecture FIRFilter of FIRFilter is
    -- registers between PEs
    signal reg_0 : signed(word_size-1 downto 0);
    signal reg_1 : signed(word_size-1 downto 0);
    signal reg_2 : signed(word_size-1 downto 0);

begin

    process (clk)
    begin 
        if clk'event and clk='1' then
            reg_0 <= (x_in * a_0) + 0;
        end if;
    end process;

    process (clk)
    begin 
        if clk'event and clk='1' then
            reg_1 <= (x_in * a_1) + reg_0;
        end if;
    end process;

    process (clk)
    begin 
        if clk'event and clk='1' then
            reg_2 <= (x_in * a_2) + reg_1;
        end if;
    end process;

    y_out <= (x_in * a_3) + reg_2;
    

end architecture;
